1. Field of the Invention
The present invention generally relates to a semiconductor memory device and, more particularly, to the designation of its operation mode from the outside. The present invention has particular applicability for externally designating a self refresh mode in a dynamic random access memory.
2. Description of the Background
Recently, personal computers came to be widely used. Particularly at present, a demand for portable personal computers is being increased. A memory device used in such a portable personal computer needs to be backed up by a battery and to have low power consumption. As a memory device in such use, a static random access memory or a dynamic random access memory (hereinafter referred to as a DRAM) is used.
In the DRAM, each memory cell comprises one transistor and one capacitor. This is called a one-transistor/one-capacitor type memory cell in which the cell area can be made small so that it is suitable for implementing a high degree of integration.
Since the memory cell comprises one transistor and one capacitor, if the DRAM has been placed in a standby state for a long time, an electric charge stored in the capacitor will be gradually lost due to a junction leak and the like. Therefore, it is necessary to read a stored signal and then rewrite it after a certain period of time. Its operation is called a refresh and there are two modes for performing this operation. First is a RAS only refresh mode in which the refresh operation is performed by externally applying a RAS signal and a row address signal. Second, is a CAS before RAS (automatic) refresh mode in which only RAS and CAS signals are externally applied and the refresh mode is performed using a signal outputted from an address counter provided inside. Assume that these refresh modes are referred to as a common refresh mode in the following description.
When the DRAM is used in the apparatus having the above mentioned battery backup function, the DRAM should be placed in the standby state while it is backed up by a battery. Therefore, it is necessary to perform the refresh operation at a certain period of time. In order to perform the refresh operation in the above mentioned common refresh mode, it is necessary to control (toggle) the RAS and CAS signals every cycle. In order to perform the refresh operation in such a common refresh mode while the battery backup is performed, it is necessary to provide a circuit which controls the timing of the RAS and CAS signals and outputs them, whereby the size of the apparatus becomes large and power consumption is increased.
In order to solve this problem, a DRAM having a self refresh mode was proposed and is commercially available. One example of the the self refresh mode is disclosed in, for example a paper entitled "A 64K bit MOS Dynamic RAM having an Automatic/Self Refresh Function" by Yamada et al. (pp. 62 to 69, No. 1, J66-C Vol., in January 1983 of Journal of Institute of Electronics and Communication Engineers of Japan).
FIG. 4 is a block diagram showing one example of a conventional DRAM having a self refresh mode. Referring to FIG. 4, the DRAM comprises a memory cell array 97 including memory cells, an address buffer 96 for temporarily storing an address signal, and a row decoder 98 for decoding the address signal. An address switching circuit 95 is connected to receive external address signals A.sub.0 to A.sub.7 and refresh address signals Q.sub.0 to Q.sub.6 generated inside and outputs either address signal to the address buffer 96 in response to a refresh control circuit 92. A detection circuit 91 is provided for detecting the self refresh mode and the refresh control circuit 92 operates a timer 93 and a refresh address counter 94 in response to the detection of the self refresh mode.
In operation, if an external RAS signal at a high level is applied (in the standby state) and an external refresh signal REF continues to remain at a low level more than a predetermined time (maximum is 16.mu.s), the designation of the self refresh mode is detected by the circuit 91. The refresh control circuit 92 operates the timer 93 in response to this detection. The timer 93 outputs a signal to the refresh address counter 94 through the circuit 92 at least every 16.mu.s. The refresh address signals Q.sub.0 to Q.sub.6 outputted from the counter 94 are applied to the row decoder through the address switching circuit 95 and the address buffer 96. The row decoder 98 decodes the signals Q.sub.0 to Q.sub.6, a word line in the memory array 97 is sequentially selected and a data signal stored in the memory cell is refreshed. As long as the signal REF remains at a low level, the refresh operation in the self refresh mode is continued.
FIG. 5A is a block diagram showing another example of a conventional DRAM having the self refresh mode. FIG. 5B is a timing chart for describing its operation. These figures are disclosed in Japanese Patent Laying-Open Gazette No. 57097/1986.
Referring to FIG. 5A, it should be noted that the external refresh signal REF is not required when the self refresh mode is externally designated in this DRAM. That is, a refresh timing generation circuit 25 connected to a timer 24 detects the self refresh mode in response to the RAS signal. More specifically, as shown in FIG. 5B, after the refresh timing generation circuit 25 detects the CAS before RAS refresh mode, it detects that the RAS signal remains at a low level more than a predetermined period of time and, then the designation of the self refresh mode is determined. The refresh operation after the recognition of the self refresh mode is the same as that of the DRAM shown in FIG. 4, so that the description thereof is omitted.
The DRAM shown in FIG. 4 is not preferable because it needs a terminal receiving the external refresh signal REF for designating the self refresh mode. In addition, the DRAM shown in FIG. 5A has a problem in which the timing of the CAS before RAS refresh to be defined is limited because the self refresh mode is detected by the RAS signal.
A further example of a prior art of interest to the present invention is seen in U.S. Pat. No. 4,636,989 filed Jan. 13, 1987 on behalf of Ikuzaki, entitled "Dynamic MOS Random Access Memory". This prior art, discloses the DRAM which starts refresh operation if the RAS signal remains at a high level more than a predetermined period of time. This example is not preferred as described above because a timing of change of the externally applied RAS signal is limited.